In typical semiconductor device applications, numerous devices are packed into a small area of a semiconductor substrate to create an integrated circuit. Many of the individual devices are electrically isolated from one another. Accordingly, electrical isolation is an integral part of semiconductor device design for preventing unwanted electrical coupling between adjacent components and devices.
Conventional methods of isolating circuit components typically use trench isolation regions. Such are formed by depositing or otherwise forming a masking layer over a semiconductor substrate. Trenches are etched through the masking layer into the semiconductor substrate, with the trenches being subsequently filled with insulative material. Exemplary masking materials for trench isolation include silicon nitride and polysilicon with or without an underlying pad oxide layer. Further after forming the trenches, they are typically lined with silicon nitride which ultimately forms part of the trench isolation material. Sidewalls of the trenches are typically oxidized as well to form silicon dioxide and either before or after the nitride liner deposition.
The trench isolation material which is formed in the isolation trenches typically includes deposition of insulative material over the masking material and to within the trenches, typically over-filling them. The isolation material is typically then polished back, for example by chemical-mechanical polishing, at least to the outer surface of the masking material. The masking material is then typically selectively etched away from the substrate leaving, at least at this point in the process, insulative isolation material filling and extending outwardly of the trench isolation regions. Unfortunately where the masking material comprises silicon nitride and where silicon nitride is also utilized to line the trenches, the nitride liner might get etched as well. This can cause nitride liner recessing within the trenches relative to the outer surface of the semiconductive material of the substrate. This can result in gate oxide wrap-around that can degrade the transistors which are ultimately fabricated.
While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.